1. Field of the Invention
The present invention relates to a semiconductor storage device and, more particularly, a semiconductor storage device which operates synchronously with an external clock signal.
2. Description of the Background Art
In association with increase in operating speed of a microprocessor (hereinbelow, called an MPU) of recent years, to realize high-speed access of a dynamic random access memory (hereinbelow, called a DRAM) or the like used as a main storage device, a synchronous DRAM (hereinbelow, referred to as an SDRAM) or the like which operates synchronously with a clock signal is used.
In an earlier DRAM which does not yet have such a configuration that it operates synchronously with a clock signal, data is outputted from the DRAM within predetermined time (access time) since a timing clock received from the outside.
An SDRAM or the like which operates synchronously with a clock signal has a feature such that, even when its operation becomes faster and a data window of data outputted from a semiconductor storage device becomes narrow, data is received from the outside synchronously with a rising edge of a clock, so that a data read error hardly occurs.
Depending on a system to which a semiconductor storage device is used, however, the semiconductor storage device is requested to operate at a higher speed.
In order to address such a request of increase in processing speed, for example, what is called a double data rate SDRAM (hereinbelow, called a DDR-SDRAM) of providing a timing of data output by using not only a rising edge of a clock but also a trailing edge has been realized.
To realize an operation of such an SRAM, DDR-SDRAM, or the like, a delay locked loop circuit (hereinbelow, referred to as a DLL circuit) is used for generating an internal clock signal synchronized with the external clock signal.
When the DLL circuit is used, however, a problem such that power consumption in a power down mode and the like increases arises.
FIG. 12 is a schematic block diagram for explaining the configuration of such a conventional DLL circuit 2000.
The DLL circuit 2000 has an external clock buffer 2002 for receiving and buffering an external clock signal ext.CLK supplied from the outside, a delay circuit 2010 for receiving an output from the external clock buffer 2002, delaying the output by delay time variably changed and set, and outputting the delayed signal as an internal clock signal int.CLK, a replica delay circuit 2020 for receiving the output of the delay circuit 2010 and delaying the output by predetermined time for adjusting the phase of the internal clock signal int.CLK, a phase comparator 2030 for receiving the output of the external clock buffer 2002 and the output of the replica delay circuit 2020, comparing the phases of the outputs with each other, and outputting a control signal SUP or SDOWN in accordance with the result of comparison, an address generating circuit 2040 for generating a control signal for controlling a delay amount of the delay circuit 2010 so that the phase of the output from the replica delay circuit 2020 and that from the external clock buffer 2002 synchronize with each other in accordance with the signal SUP or SDOWN from the phase comparator 2030, and an address decoder 2050 for receiving an output from the address generating circuit 2040 and outputting a decode signal for controlling the delay amount of the delay circuit 2010.
The replica delay circuit 2020 has, for example, a configuration similar to that of the external clock buffer 2002. With such a configuration, the external clock signal ext.CLK is passed through the external clock buffer 2002 and, after that, supplied to the phase comparator 2030. The internal clock signal int.CLK outputted from the delay circuit 2010 is passed through the replica delay circuit 2020 and then applied to the phase comparator 2030. When the phase comparator 2030 compares the phases of the signals and controls the delay amount of the delay circuit 2010 on the basis of a phase difference so as to eliminate the phase difference, synchronization between the external clock signal ext.CLK and the internal clock signal int.CLK can be basically achieved.
In practice, the internal clock signal int.CLK is outputted from the delay circuit 2010 and is supplied to a buffer circuit for receiving an external control signal and an external address signal, or the like. In this case, when an amplification level of the external clock signal ext.CLK, the ratio of an active period of the clock signal to its cycle, or the like is different from a corresponding amount of the internal clock signal int.CLK, to adjust the difference, the replica delay circuit 2020 may have a delay amount different from that of the external clock buffer 2002 only by an amount of the adjustment.
In an SDRAM having the DLL circuit as shown in FIG. 12, the DLL circuit 2000 operates also in a power down mode (period in which a signal CKE is at an inactive level (xe2x80x9cLxe2x80x9d level)) of the SDRAM for the following reason.
When the operation of the DLL circuit 2000 is once stopped, after recovery from the power down mode to a normal mode, it takes, for example, about 200 cycles for the delay circuit 2010 in the DLL circuit 2000 to recover to a state where the delay circuit 2010 can make the phase of the external clock signal ext.CLK and that of the internal clock signal int.CLK synchronize with each other. Consequently, a data reading operation or the like cannot be performed immediately after recovery to the normal mode.
In order to deal with such a problem, it is also possible to hold the value of a decode signal supplied to the delay circuit 2010 in the DLL circuit 2000 just before the SDRAM enters the power down mode and, when the SDRAM recovers to the normal mode, to start the operation by using the value of the decode signal as an initial value.
In such a configuration, however, when a delay characteristic of the delay circuit 2010 changes due to a temperature change, voltage change, or the like during the DLL circuit 2000 is suspended, the held delay information becomes useless.
As a result, considerable time is necessary for the delay circuit 2010 in the DLL circuit 2000 to recover to a state where the delay circuit 2010 can synchronize the phases.
In this case, the required time for recovery depends on the degree of the temperature change, voltage change, or the like which occurs during the power down mode, so that it cannot be specified in advance. In order to assure that the data reading operation or the like can be performed immediately after the SDRAM is recovered from the power down mode to the normal mode, therefore, the DLL circuit has to be operated also during the power down mode.
As a result, inherently, in spite of the power down mode for the SDRAM, power is additionally consumed.
An object of the invention is to provide a semiconductor storage device with suppressed power consumption also in a power down mode.
According to the invention, there is provided a semiconductor storage device which performs a synchronous operation on the basis of an external clock signal, having a storage circuit, a clock control signal generating circuit, and an internal clock signal generating circuit.
The storage circuit holds storage data. The clock control signal generating circuit generates an internal control signal which is intermittently active in a suspension mode in which data transmitting/receiving operations between the storage circuit and the outside of the semiconductor storage device are suspended according to a control signal from the outside, and which is active in a normal mode. The internal clock signal generating circuit is made active by the internal control signal, receives the external clock signal, and generates an internal clock signal for controlling data transmitting/receiving operations to/from the storage circuit.
Therefore, an advantage of the invention is that power consumption in the suspend period is reduced and the internal clock signal generating circuit can generate a desired internal clock signal in short period of time after recovery from the suspension period to normal operation. A data reading operation and the like can be performed in short period of time after recovery from the suspension period to normal operation.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.